Blue Visions Technologies Vlsi Bv001vlsi14 Design Flow for Flip-flop Grouping in Data-driven Clock Gating

Clock gating is a predominant technique used for power saving. It is observed that the commonly used synthesis-based gating still leaves a large amount of redundant clock pulses. Data-driven gating aims to disable these. To reduce the hardware overhead involved, flip-flops (FFs) are grouped so that they share a common clock enabling signal. The question of what is the group size maximizing the power savings is answered in a previous paper. Here we answer the question of which FFs should be placed in a group to maximize the power reduction. We propose a practical solution based on the toggling activity correlations of FFs and their physical position proximity constraints in the layout. Our datadriven clock gating is integrated into an Electronic Design Automation (EDA) commercial backend design flow, achieving total power reduction of 15%–20% for various types of large-scale state-of-the-art industrial and academic designs in 40 and 65 manometer process technologies. These savings are achieved on top of the savings obtained by clock gating synthesis performed by commercial EDA tools, and gating manually inserted into the register transfer level design. BV002VLSI13 NEW HIGH-SPEED MULTIOUTPUT CARRY LOOK-AHEAD ADDERS Abstract—In this brief, an efficient implementation of an 8-bit Manchester carry chain (MCC) adder in multioutput domino CMOS logic is proposed. The carries of this adder are computed in parallel by two independent 4-bit carry chains. Due to its limited carry chain length, the use of the proposed 8-bit adder module for the implementation of wider adders leads to significant operating speed improvement compared to the corresponding adders based on the standard 4-bit MCC adder module.In this brief, an efficient implementation of an 8-bit Manchester carry chain (MCC) adder in multioutput domino CMOS logic is proposed. The carries of this adder are computed in parallel by two independent 4-bit carry chains. Due to its limited carry chain length, the use of the proposed 8-bit adder module for the implementation of wider adders leads to significant operating speed improvement compared to the corresponding adders based on the standard 4-bit MCC adder module. BV003VLSI14 A FULLY STATIC TOPOLOGICALLY-COMPRESSED 21-TRANSISTOR FLIP-FLOP WITH 75% POWER SAVING Abstract—An extremely low-power flip-flop (FF) named topo-logically-compressed flip-flop (TCFF) is proposed. As compared with conventional FFs, the FF reduces power dissipation by 75% at 0% data activity. This power reduction ratio is the highest among FFs that have been reported so far. The reduction is achieved by applying topological compression method, merger of logically equivalent transistors to an unconventional latch structure. The very small number of transistors, only three, connected to clock signal reduces the power drastically, and the smaller total transistor count assures the same cell area as conventional FFs. In addition, fully static full-swing operation makes the cell tolerant of supply voltage and input slew variation. An experimental chip design with 40 nm CMOS technology showsAn extremely low-power flip-flop (FF) named topo-logically-compressed flip-flop (TCFF) is proposed. As compared with conventional FFs, the FF reduces power dissipation by 75% at 0% data activity. This power reduction ratio is the highest among FFs that have been reported so far. The reduction is achieved by applying topological compression method, merger of logically equivalent transistors to an unconventional latch structure. The very small number of transistors, only three, connected to clock signal reduces the power drastically, and the smaller total transistor count assures the same cell area as conventional FFs. In addition, fully static full-swing operation makes the cell tolerant of supply voltage and input slew variation. An experimental chip design with 40 nm CMOS technology shows that almost all con-ventional FFs are replaceable with proposed FF while preserving the same system performance and layout area. BV004VLSI15 HIGH-SPEED AND ENERGY-EFFICIENT CARRY SKIP ADDER OPERATING UNDER A WIDE RANGE OF SUPPLY VOLTAGE LEVELS Abstract— In this paper, we present a carry skip adder (CSKA) structure that has a higher speed yet lower energy consumption compared with the conventional one. The speed enhancement is achieved by applying concatenation and incrementation schemes to improve the efficiency of the conventional CSKA (Conv-CSKA) structure. In addition, instead of utilizing multiplexer logic, the proposed structure makes use of AND-OR-Invert (AOI) and OR-AND-Invert (OAI) compound gates for the skip logic. The structure may be realized with both fixed stage size and variable stage size styles, wherein the latter further improves the In this paper, we present a carry skip adder (CSKA) structure that has a higher speed yet lower energy consumption compared with the conventional one. The speed enhancement is achieved by applying concatenation and incrementation schemes to improve the efficiency of the conventional CSKA (Conv-CSKA) structure. In addition, instead of utilizing multiplexer logic, the proposed structure makes use of AND-OR-Invert (AOI) and OR-AND-Invert (OAI) compound gates for the skip logic. The structure may be realized with both fixed stage size and variable stage size styles, wherein the latter further improves the speed and energy parameters of the adder. Finally, a hybrid variable latency extension of the proposed structure, which lowers the power consumption without considerably impacting the speed is presented. This extension utilizes a modified parallel structure for increasing the slack time, and hence, enabling further voltage reduction. The proposed structures are assessed by comparing their speed, power, and energy parameters with those of other adders using a 45-nm static CMOS technology for a wide range of supply voltages. The results that are obtained using HSPICE simulations reveal, on average, 44% and 38% improvements in the delay and energy, respectively, compared with those of the Conv-CSKA. In addition, the power–delay product was the lowest among the structures considered in this paper, while its energy–delay product was almost the same as that of the Kogge–Stone parallel prefix adder with considerably smaller area and power consumption. Simulations on the proposed hybrid variable latency CSKA reveal reduction in the power consumption compared with the latest works in this field while having a reasonably high speed. BV005VLSI15 DESIGN OF A LOW POWER 4X4 MULTIPLIER BASED ON FIVE TRANSISTOR (5T) HALF ADDER, EIGHT TRANSISTOR (8-T) FULL ADDER & TWO TRANSISTOR (2-T) AND GATE Abstract— In this paper, we propose a new technique for implementing a low power high speed multiplier using full adder consisting of minimum no. of transistors (8-T). Multiplier circuits are used comprehensively in Application Specific Integrated Circuits (ASICs). Thus it is desirable to have high speed operation for the sub components. The explored method of In this paper, we propose a new technique for implementing a low power high speed multiplier using full adder consisting of minimum no. of transistors (8-T). Multiplier circuits are used comprehensively in Application Specific Integrated Circuits (ASICs). Thus it is desirable to have high speed operation for the sub components. The explored method of implementation achieves a high speed low power design for the multiplier. Simulated results indicate the superior performance of the proposed technique over conventional CMOS multiplier. Detailed comparison of simulated results for the conventional and present method of implementation is presented. BV006VLSI15 ENERGY AND AREA EFFICIENT THREE-INPUT XOR/XNORS WITH SYSTEMATIC CELL DESIGN METHODOLOGY Abstract— In this brief, we propose three efficient three-input XOR/XNOR circuits as the most significant blocks of digital systems with a new systematic cell design methodology (SCDM) in hybrid-CMOS logic style. SCDM, which is an extension of CDM, plays the essential role in designing efficient circuits. At first, it is deliberately given priority to general design goals in a base structure of circuits. This structure is generated systematically by employing binary decision diagram. After that, concerning high flexibility in design targets, SCDM aims to specific ones in the remaining three steps, which are wise selections of basic cells and amend mechanisms, as well as transistor sizing. In the end, the resultant three-input XOR/XNORs enjoy full-swing and fairly balanced outputs. They perform well with supply voltage scaling, and their critical path contains only two transistors. They also outperform their counterparts exhibiting 27%–77% reduction in average energy-delay product in HSPICE simulation based on TSMC 0.13-μm technology. The symmetric schematic topologies In this brief, we propose three efficient three-input XOR/XNOR circuits as the most significant blocks of digital systems with a new systematic cell design methodology (SCDM) in hybrid-CMOS logic style. SCDM, which is an extension of CDM, plays the essential role in designing efficient circuits. At first, it is deliberately given priority to general design goals in a base structure of circuits. This structure is generated systematically by employing binary decision diagram. After that, concerning high flexibility in design targets, SCDM aims to specific ones in the remaining three steps, which are wise selections of basic cells and amend mechanisms, as well as transistor sizing. In the end, the resultant three-input XOR/XNORs enjoy full-swing and fairly balanced outputs. They perform well with supply voltage scaling, and their critical path contains only two transistors. They also outperform their counterparts exhibiting 27%–77% reduction in average energy-delay product in HSPICE simulation based on TSMC 0.13-μm technology. The symmetric schematic topologies significantly simplify and minimize the layout, as 26%–32% improvement in area is demonstrated. BV007VLSI14 DEVELOPMENT OF AN FPGA-BASED SPWM GENERATOR FOR HIGH SWITCHING FREQUENCY DC/AC INVERTERS Abstract—The digital implementations of Sinusoidal Pulse Width Modulation (SPWM) generators have dominated over their counterparts based on analog circuits. In this paper, an FPGAbased SPWM generator is presented, which is capable to operate at switching frequencies up to 1 MHz (requiring FPGA operation at 100–160 MHz), thus it is capable to support the high switching frequency requirements of modern single-phase dc/ac power converters. The proposed design occupies a small fraction of a medium-sized FPGA and, thus, can be incorporated in larger de-signs. Additionally, it has a flexible architecture that can be tuned to a variety of single-phase dc/ac inverter applications. The postlayout simulation and experimental results confirm that compared to the past-proposed SPWM generation designs, the SPWM generator presented in this paper exhibits much faster switching frequency, lower power consumption, and higher accuracy of generating the desired SPWM waveform.The digital implementations of Sinusoidal Pulse Width Modulation (SPWM) generators have dominated over their counterparts based on analog circuits. In this paper, an FPGAbased SPWM generator is presented, which is capable to operate at switching frequencies up to 1 MHz (requiring FPGA operation at 100–160 MHz), thus it is capable to support the high switching frequency requirements of modern single-phase dc/ac power converters. The proposed design occupies a small fraction of a medium-sized FPGA and, thus, can be incorporated in larger de-signs. Additionally, it has a flexible architecture that can be tuned to a variety of single-phase dc/ac inverter applications. The postlayout simulation and experimental results confirm that compared to the past-proposed SPWM generation designs, the SPWM generator presented in this paper exhibits much faster switching frequency, lower power consumption, and higher accuracy of generating the desired SPWM waveform. BV008VLSI15 NOVEL FPGA IMPLEMENTATION OF HAND SIGN RECOGNITION SYSTEM WITH SOM–HEBB CLASSIFIER Abstract— This paper proposes a hardware posture recognition system with a hybrid network. The hybrid network consists of self-organizing map (SOM) and Hebbian network. This paper proposes a hardware posture recognition system with a hybrid network. The hybrid network consists of self-organizing map (SOM) and Hebbian network. Feature vectors are extracted from input posture images, which are mapped to a lower dimensional map of neurons in the SOM. The Hebbian network is a single-layer feedforward neural network trained with a Hebbian learning algorithm to identify categories. The recognition algorithm is robust to the change in location of hand signs, but it is not immune to rotation or scaling. Its robustness to rotation and scaling was improved by adding perturbation to the training data for the SOM–Hebb classifier. In addition, neuron culling is proposed to improve performance. The whole system is implemented on a fieldprogrammable gate array employing novel video processing architecture. The system was designed to recognize 24 American sign language hand signs, and its feasibility was verified through both simulations and experiments. The experimental results revealed that the system could accomplish recognition at a speed of 60 frames/s, while achieving an accuracy of 97.1%. Due to a novel hardware implementation, the circuit size of the proposed system is very small, which is highly suitable for embedded applications. BV009VLSI14 DESIGN OF LOW POWER AND HIGH SPEED MODIFIED CARRY SELECT ADDER FOR 16 BIT VEDIC MULTIPLIER Abstract— In this paper, a high speed and low power 16x16Vedic Multiplier is designed by using low power and high speed modified carry select adder. Modified Carry Select Adder employs a newly incremented circuit in the intermediate stages of the Carry Select Adder In this paper, a high speed and low power 16x16Vedic Multiplier is designed by using low power and high speed modified carry select adder. Modified Carry Select Adder employs a newly incremented circuit in the intermediate stages of the Carry Select Adder (CSA) which is known to be the fastest adder among the conventional adder structures. A Novel technique for digit multiplication namely Vedic multiplication has been introduced which is quite different from normal multiplication by shift and addition operations. Normally a multiplier is a key block in almost all the processors and also introduces high delay block and also a major power dissipation source. This paper presents a new design methodology for less delay and less power efficient Vedic Multiplier based up on ancient Vedic Mathematic techniques. This paper presents a technique for N×N multiplication is implemented and gives very less delay for calculating multiplication results for 16×16 Vedic multiplier. In this paper, the main goal is to design the high speed and low power and area efficient Vedic multiplier based on the crosswise and vertical algorithm. Comparisons with existing conventional fast adder architectures have been made to prove its efficiency. The performance analysis shows that the proposed architecture achieves three fold advantages in terms of delay-area-power. The synthesis results of the Vedic multiplier has compared with the booth, array multiplier by different technologies. BV010VLSI15 ENERGY-EFFICIENT APPROXIMATE MULTIPLICATION FOR DIGITAL SIGNAL PROCESSING AND CLASSIFICATION APPLICATIONS Abstract— The need to support various digital signal processing (DSP) and classification applications on energy-constrained devices has steadily grown. Such applications often extensively perform matrix multiplications using fixed-point arithmetic while exhibiting tolerance for some computational errors. Hence, improving the energy efficiency of multiplications is critical. In this brief, we propose multiplier architectures that can tradeoff The need to support various digital signal processing (DSP) and classification applications on energy-constrained devices has steadily grown. Such applications often extensively perform matrix multiplications using fixed-point arithmetic while exhibiting tolerance for some computational errors. Hence, improving the energy efficiency of multiplications is critical. In this brief, we propose multiplier architectures that can tradeoff computational accuracy with energy consumption at design time. Compared with a precise multiplier, the proposed multiplier can consume 58% less energy/op with average computational error of ∼1%. Finally, we demonstrate that such a small computational error does not notably impact the quality of DSP and the accuracy of classification applications. BV011VLSI14 AREA-DELAY-POWER EFFICIENT CARRY-SELECT ADDER Abstract—In this brief, the logic operations involved in conventional carry select adder (CSLA) and binary to excess-1 converter (BEC)-based CSLA are analyzed to study the data dependence and to identify redundant logic operations. We have eliminated all the redundant logic operations present in the conventional CSLA and proposed a new logic formulation for CSLA. In the proposed scheme, the carry select (CS) operation is scheduled before the calculation of final-sum, which is different from the conventional approach. Bit patterns of two anticipating carry words (corresponding to cin = 0 and 1) and fixed cin bits are used for logic optimization of CS and generation units. An efficient CSLA design is obtained using optimized logic units. The proposed CSLA design involves significantly less area and delay than the recently proposed BEC-based CSLA. Due to the small carry-output delay, the proposed CSLA design is a good candidate for square-root (SQRT) CSLA. A theoretical estimate shows that the proposed SQRT-CSLA involves nearly 35% less area–In this brief, the logic operations involved in conventional carry select adder (CSLA) and binary to excess-1 converter (BEC)-based CSLA are analyzed to study the data dependence and to identify redundant logic operations. We have eliminated all the redundant logic operations present in the conventional CSLA and proposed a new logic formulation for CSLA. In the proposed scheme, the carry select (CS) operation is scheduled before the calculation of final-sum, which is different from the conventional approach. Bit patterns of two anticipating carry words (corresponding to cin = 0 and 1) and fixed cin bits are used for logic optimization of CS and generation units. An efficient CSLA design is obtained using optimized logic units. The proposed CSLA design involves significantly less area and delay than the recently proposed BEC-based CSLA. Due to the small carry-output delay, the proposed CSLA design is a good candidate for square-root (SQRT) CSLA. A theoretical estimate shows that the proposed SQRT-CSLA involves nearly 35% less area– delay–product (ADP) than the BEC-based SQRT-CSLA, which is best among the existing SQRT-CSLA designs, on average, for different bit-widths. The application-specified integrated circuit (ASIC) synthesis result shows that the BEC-based SQRT-CSLA design involves 48% more ADP and consumes 50% more energy than the proposed SQRT-CSLA, on average, for different bit-widths. BV012VLSI14 FAULT TOLERANT PARALLEL FILTERS BASED ON ERROR CORRECTION CODES Abstract— Digital filters are widely used in signal processing and communication systems. In some cases, the reliability of those systems is critical, and fault tolerant filter implementations are needed. Over the years, many techniques that exploit the filters’ structure and properties to achieve fault tolerance have been proposed. As technology scales, it enables more complex systems that incorporate many filters. In those complex systems, it is common that some of the filters operate in parallel, for example, by applying the same filter to different input signals. Recently, a simple technique that exploits the presence of parallel filters to achieve fault tolerance has been presented. In this brief, that idea is generalized to show that parallel filters can be protected using error correction codes (ECCs) in which each filter is the equivalent of a bit in a traditional ECC. This new scheme allows more efficient protection when the number of parallel filters is large. The technique is evaluated using a case study of parallel finite impulse response filters showing the effectiveness in terms of protection and implementation cost. Digital filters are widely used in signal processing and communication systems. In some cases, the reliability of those systems is critical, and fault tolerant filter implementations are needed. Over the years, many techniques that exploit the filters’ structure and properties to achieve fault tolerance have been proposed. As technology scales, it enables more complex systems that incorporate many filters. In those complex systems, it is common that some of the filters operate in parallel, for example, by applying the same filter to different input signals. Recently, a simple technique that exploits the presence of parallel filters to achieve fault tolerance has been presented. In this brief, that idea is generalized to show that parallel filters can be protected using error correction codes (ECCs) in which each filter is the equivalent of a bit in a traditional ECC. This new scheme allows more efficient protection when the number of parallel filters is large. The technique is evaluated using a case study of parallel finite impulse response filters showing the effectiveness in terms of protection and implementation cost. BV013VLSI14 SINGLE-ERROR-CORRECTION AND DOUBLE-ADJACENT-ERROR-CORRECTION CODE FOR SIMULTANEOUS TESTING OF DATA BIT AND CHECK BIT ARRAYS IN MEMORIES Abstract—In this paper, a new single-error-correction and double-adjacent-error-correction (SEC-DAEC) code is proposed for simultaneous testing of the most general memory fault models in both data bit and check bit arrays of memories. Simultaneous testing of data bit and check bit arrays eliminates the test time and hardware overheads required for separate check bit array tests. In order to test data bit and check bit arrays simultaneously, the proposed SEC-DAEC code generates the identical data background patterns for data bit andIn this paper, a new single-error-correction and double-adjacent-error-correction (SEC-DAEC) code is proposed for simultaneous testing of the most general memory fault models in both data bit and check bit arrays of memories. Simultaneous testing of data bit and check bit arrays eliminates the test time and hardware overheads required for separate check bit array tests. In order to test data bit and check bit arrays simultaneously, the proposed SEC-DAEC code generates the identical data background patterns for data bit and check bit arrays. The testable faults using the proposed SEC-DAEC code are the most general memory fault models such as single-cell faults and interword and intraword coupling faults. Simultaneous testing of data bit and check bit arrays using the proposed SEC-DAEC codes brings significant decreases of about 27.3%, 17.9%, and 11.1% in the time required for memory array tests for 16, 32, and 64 data bits per word, respectively. In addition, the number of ones in the H-matrix of the proposed SEC-DAEC code is brought close to the theoretical minimum number, thereby reducing the complexity of the check bit generator. BV014VLSI08 FUNCTIONAL DESIGN OF FPGA IN A BRUSHLESS DC MOTOR SYSTEM BASED ON FPGA AND DSP Abstract—Because of its high performance, brushless DC motors are widely used in motor vehicles. In this paper, according to analysis of present motor control system, a novel hardware structure of motor control system was presented. It is based on Field Programmable Gate Arrays (FPGA) and Digital Signal Processor (DSP). According to the function needed in motor control and the structure feature of FPGA and DSP, the tasks taken by FPGA and DSP were divided. A functional design of FPGA in a brushless DC motor system based on FPGA and DSP was completed by using modular design method. All the function modules are programmed by Very-High-Speed Integrated Circuit Hardware Description Language (VHDL).The function modules implemented in FPGA were introduced in detail. The advantage of the system is its good operational performance and expansibility. The application of FPGA can greatly simplify the design of peripheral circuits and release DSP from tedious operation. The simulation and experiment results verified its validity, and it can also act as an example for the application of FPGA in motor control field.Because of its high performance, brushless DC motors are widely used in motor vehicles. In this paper, according to analysis of present motor control system, a novel hardware structure of motor control system was presented. It is based on Field Programmable Gate Arrays (FPGA) and Digital Signal Processor (DSP). According to the function needed in motor control and the structure feature of FPGA and DSP, the tasks taken by FPGA and DSP were divided. A functional design of FPGA in a brushless DC motor system based on FPGA and DSP was completed by using modular design method. All the function modules are programmed by Very-High-Speed Integrated Circuit Hardware Description Language (VHDL).The function modules implemented in FPGA were introduced in detail. The advantage of the system is its good operational performance and expansibility. The application of FPGA can greatly simplify the design of peripheral circuits and release DSP from tedious operation. The simulation and experiment results verified its validity, and it can also act as an example for the application of FPGA in motor control field. BV015VLSI12 STABILITY ANALYSIS OF FPGA-BASED CONTROL OF BRUSHLESS DC MOTORS AND GENERATORS USING DIGITAL PWM TECHNIQUE Abstract—Brushless dc (BLDC) drives have received significant attention, owing to their high efficiency, electromagnetic interference, and high mechanical reliability due to the absence of brushes in commercial, residential, and industrial applications. In generating mode, they are very suitable for small wind and hydro generator applications, as well as integrated starter alternators in hybrid electric vehicles. This paper discusses digital pulse width modulation control for a BLDC drive in both motoring and generating modes of operation. This control strategy is simple and robust, requires no current sensors, and is not computationally intensive. Owing to these attributes, the technique can be implemented on a low-cost field-programmable gate array. This paper investigates potential stability issues due to the simplicity of this control under various conditions of load disturbances and also owing to the reduction in processor capability. Lyapunov stability criteria have been used to analyze the closed-loop stability of the system. Furthermore, an approximate discrete model has been developed, and the stability of the system is analyzed to ensure closed-loop operation under various sets of loads, speeds, and input voltages. Simulation and experimental results have been presented to verify the claims.Brushless dc (BLDC) drives have received significant attention, owing to their high efficiency, electromagnetic interference, and high mechanical reliability due to the absence of brushes in commercial, residential, and industrial applications. In generating mode, they are very suitable for small wind and hydro generator applications, as well as integrated starter alternators in hybrid electric vehicles. This paper discusses digital pulse width modulation control for a BLDC drive in both motoring and generating modes of operation. This control strategy is simple and robust, requires no current sensors, and is not computationally intensive. Owing to these attributes, the technique can be implemented on a low-cost field-programmable gate array. This paper investigates potential stability issues due to the simplicity of this control under various conditions of load disturbances and also owing to the reduction in processor capability. Lyapunov stability criteria have been used to analyze the closed-loop stability of the system. Furthermore, an approximate discrete model has been developed, and the stability of the system is analyzed to ensure closed-loop operation under various sets of loads, speeds, and input voltages. Simulation and experimental results have been presented to verify the claims. BV016VLSI13 FPGA BASED SPEED CONTROL OF BRUSHLESS DC MOTORS USING IOPT PETRI NET MODELS This paper describes how to implement a functional Brushless DC Motor open-loop speed controller from simple IOPT Petri Net models, using the integrated development environment offered by IOPT-Tools, without the need to manually write software or hardware descriptions. IOPT nets are a Petri net class specifically designed to support the implementation of embedded system controllers. The IOPT-Tools Web service (http://gres.uninova.pt) includes an interactive graphical editor to design IOPT models, a model checking framework consisting of a state-space generator and a query system, and automatic code generation tools to produce software (C) or hardware (VHDL) controller implementations. The Brushless DC Motor speed controller was decomposed into several subsystems, including a noise filter, quadrature-decoder, PWM generator and an BLDC commutation-manager. These sub-systems were modelled using simple IOPT models, analysed using the model-checking tools, resulting in the automatic creation of VHDL modules for each sub-system. To finish the entire project, a top VHDL module is used to instantiate copies of the automatically generated components and specify signals to connect the components to the external world. With the addition of an inverter board, a working prototype was implemented and successfully tested. BV017VLSI13 REAL TIME FPGA IMPLEMENTATION OF BRUSHLESS DC MOTOR CONTROL USING SINGLE CURRENT SENSOR Abstract— In modern industry power consumption is becoming one of the most important constraints during the development phase of the product. In motor industry, significant part of the power consumption improvement can be done in motor control. Brushless dc (BLDC) motor drives are penetrating the market rapidly. Heating, ventilation and air conditioning (HVAC) systems use conventional motor drive technology and the machines found in these devices are characterized by low efficiency and high maintenance. BLDC motor drives are characterized by higher efficiency, lower maintenance and higher cost. This paper presents the analysis, design, and implementation of a cost-effective control technique for a low cost solution, six switch three-phase inverter brushless dc motor drive using single current sensor for current control. Various parameters defined optimization path for target drive solution. Also, basic framework for low cost BLDC control IC is presented. The controller is modeled and the concept is proven using simulator. Then the verification and feasibility study are done by using field-programmable gate array prototyping on the custom board made for this research. Final simulation results along with prototype operation measurements are presented as well. In modern industry power consumption is becoming one of the most important constraints during the development phase of the product. In motor industry, significant part of the power consumption improvement can be done in motor control. Brushless dc (BLDC) motor drives are penetrating the market rapidly. Heating, ventilation and air conditioning (HVAC) systems use conventional motor drive technology and the machines found in these devices are characterized by low efficiency and high maintenance. BLDC motor drives are characterized by higher efficiency, lower maintenance and higher cost. This paper presents the analysis, design, and implementation of a cost-effective control technique for a low cost solution, six switch three-phase inverter brushless dc motor drive using single current sensor for current control. Various parameters defined optimization path for target drive solution. Also, basic framework for low cost BLDC control IC is presented. The controller is modeled and the concept is proven using simulator. Then the verification and feasibility study are done by using field-programmable gate array prototyping on the custom board made for this research. Final simulation results along with prototype operation measurements are presented as well. BV018VLSI13 EFFICIENT METHOD FOR CONTROLLING ELECTRIC POWER BY AUTOMATED MONITORING SYSTEM USING FPGA Abstract – Power is considered to be as major concern in today’s technology. Several research works are carried in order to minimize the usage of electric power. In this paper, an efficient automated power saving system was designed using Spartan-6 FPGA for minimizing the power wastage in educational institutions. Mostly, the students forget to switch off the electrical appliances, when they leaving out of classroom. The power wastage can be completely eliminated by using this Automated Power Saving System. The system is developed by VHDL and it is implemented using Wipro Mission10x UTLP Board. Power is considered to be as major concern in today’s technology. Several research works are carried in order to minimize the usage of electric power. In this paper, an efficient automated power saving system was designed using Spartan-6 FPGA for minimizing the power wastage in educational institutions. Mostly, the students forget to switch off the electrical appliances, when they leaving out of classroom. The power wastage can be completely eliminated by using this Automated Power Saving System. The system is developed by VHDL and it is implemented using Wipro Mission10x UTLP Board. BV019VLSI13 IMPLEMENTATION OF FPGA BASED CONTROLLER FOR INDUCTION MOTOR DRIVES Abstract-This paper presents a control scheme of single phase to three phase converters for low power three phase induction motor drives, with reduced number of switching devices. Here a single phase half-bridge PWM rectifier and two-leg inverter are used with the same function that are all given by conventional one such as sinusoidal input current, unity power factor, bidirectional power flow, dc-link voltage control. Hence the number of switching devices is reduced from ten to six. A current controller is introduced for two-leg inverter. In addition, the source voltage sensor elimination technique is presented which makes the system cheaper. The effectiveness of the proposed control scheme is verified by experimental results for the VI f control of 3-HP induction motor drives with FPGA based controller.This paper presents a control scheme of single phase to three phase converters for low power three phase induction motor drives, with reduced number of switching devices. Here a single phase half-bridge PWM rectifier and two-leg inverter are used with the same function that are all given by conventional one such as sinusoidal input current, unity power factor, bidirectional power flow, dc-link voltage control. Hence the number of switching devices is reduced from ten to six. A current controller is introduced for two-leg inverter. In addition, the source voltage sensor elimination technique is presented which makes the system cheaper. The effectiveness of the proposed control scheme is verified by experimental results for the VI f control of 3-HP induction motor drives with FPGA based controller. BV020VLSI15 FAULT TOLERANT PARALLEL FFTS USING ERROR CORRECTION CODES AND PARSEVAL CHECKS Abstract— Soft errors pose a reliability threat to modern electronic circuits. This makes protection against soft errors a requirement for many applications. Communications and signal processing systems are no exceptions to this trend. For some applications, an interesting option is to use algorithmic-based fault tolerance (ABFT) techniques that try to exploit the algorithmic properties to detect and correct errors. Signal processing and communication applications are well suited for ABFT. One example is fast Fourier transforms (FFTs) that are a key building block in many systems. Several protection schemes have been proposed to detect and correct errors in FFTs. Among those, probably the uses of the Parseval or sum of squares check is the most widely known. In modern communication systems, it is increasingly common to find several blocks operating in parallel. Recently, a technique that exploits this fact to implement fault tolerance on parallel filters has been proposed. In this brief, this technique is first applied to protect FFTs. Then, two improved protection schemes that combine the use of error correction codes and Parseval checks are proposed and evaluated. The results show that the proposed schemes can further reduce the implementation cost of protection. Soft errors pose a reliability threat to modern electronic circuits. This makes protection against soft errors a requirement for many applications. Communications and signal processing systems are no exceptions to this trend. For some applications, an interesting option is to use algorithmic-based fault tolerance (ABFT) techniques that try to exploit the algorithmic properties to detect and correct errors. Signal processing and communication applications are well suited for ABFT. One example is fast Fourier transforms (FFTs) that are a key building block in many systems. Several protection schemes have been proposed to detect and correct errors in FFTs. Among those, probably the uses of the Parseval or sum of squares check is the most widely known. In modern communication systems, it is increasingly common to find several blocks operating in parallel. Recently, a technique that exploits this fact to implement fault tolerance on parallel filters has been proposed. In this brief, this technique is first applied to protect FFTs. Then, two improved protection schemes that combine the use of error correction codes and Parseval checks are proposed and evaluated. The results show that the proposed schemes can further reduce the implementation cost of protection. BV021VLSI12 DESIGN OF LOW POWER ALU USING 8T FA AND PTL BASED MUX CIRCUITS Abstract-In this paper we proposed an ALU using Novel 8T full adder and Pass transistor logic based multiplexers. A 4xl and a 2xl multiplexer were used to design an ALU. Full adder is an essential component for designing all types of processors like digital signal processors (DSP), microprocessors etc. In existing method full adder and multiplexers were designed using transmission gate logic. To reduce the number of transistors multiplexers were designed using pass transistor logic and the full adder is designed using 8 transistors. Full adder is designed using 8 transistor logic and multiplexers were designed using pass transistor logic and this is used in the implementation of ALU. In the implementation of ALU, the power and the area were greatly reduced to more than 70% compared to the existing method.In this paper we proposed an ALU using Novel 8T full adder and Pass transistor logic based multiplexers. A 4xl and a 2xl multiplexer were used to design an ALU. Full adder is an essential component for designing all types of processors like digital signal processors (DSP), microprocessors etc. In existing method full adder and multiplexers were designed using transmission gate logic. To reduce the number of transistors multiplexers were designed using pass transistor logic and the full adder is designed using 8 transistors. Full adder is designed using 8 transistor logic and multiplexers were designed using pass transistor logic and this is used in the implementation of ALU. In the implementation of ALU, the power and the area were greatly reduced to more than 70% compared to the existing method. BV022VLSI12 SDMLP: ON THE USE OF COMPLEMENTARY PASS TRANSISTOR LOGIC FOR DESIGN OF DPA RESISTANT CIRCUITS Abstract—The emergence and proliferation of Smart Cards and other security-centric technologies require ongoing advancement in secure-IC design. We propose advanced IC protection from Differential Power Analysis attack though a hybrid-logic style based on Complementary Pass-transistor and Dynamic and Differential Logic (DDL) in conjunction with a synthesis methodology based on Reduced Ordered Binary Decision Diagrams. We demonstrate the capabilities of our logic cell and compare it with Wave Dynamic Differential Logic, and the traditional Standard Complementary Logic (SCMOS). Experimental results on a DES layout show significant reduction in area (43%) and total power (50%) and near constant power consumption in every cycle when compared to existing DDL styles at a speed penalty (20%) against SCMOS.The emergence and proliferation of Smart Cards and other security-centric technologies require ongoing advancement in secure-IC design. We propose advanced IC protection from Differential Power Analysis attack though a hybrid-logic style based on Complementary Pass-transistor and Dynamic and Differential Logic (DDL) in conjunction with a synthesis methodology based on Reduced Ordered Binary Decision Diagrams. We demonstrate the capabilities of our logic cell and compare it with Wave Dynamic Differential Logic, and the traditional Standard Complementary Logic (SCMOS). Experimental results on a DES layout show significant reduction in area (43%) and total power (50%) and near constant power consumption in every cycle when compared to existing DDL styles at a speed penalty (20%) against SCMOS. BV023VLSI12 NOVEL ULTRA LOW-VOLTAGE AND HIGH-SPEED CMOS PASS TRANSISTORLOGIC In this paper we present a novel CMOS pass transistor logic style for ultra low-voltage and high speed digital applications. The circuits presented offer more than 90% delay reduction compared to conventional CMOS for supply voltages less than 400mV . Differential AND and NAND pass transistor gates presented and compared to complementary pass transistor logic CPL. Simulated data obtained by the Hspice simulation and relevant for 90nm TSMC process are provided. BV024VLSI12 ENERGY-DELAY EFFICIENT ASYNCHRONOUS-LOGIC 16×16-BIT PIPELINED MULTIPLIER BASED ON SENSE AMPLIFIER-BASED PASS TRANSISTOR LOGIC Abstract—We describe an asynchronous-logic (async) 16×16-bit pipelined multiplier based on our proposed Sense Amplifier-Based Pass Transistor Logic (SAPTL) with emphases on high energy-delay efficiency. The multiplier is targeted for an async multi-core System-On-Chip (SOC). This attribute is achieved by simplifying and optimizing the NMOS pass transistor stacks and decision-making C-element, therein to reduce the circuit area overheads and transistor switching’s in SAPTL. Based on the simulations (@1V, 65nm CMOS process), theWe describe an asynchronous-logic (async) 16×16-bit pipelined multiplier based on our proposed Sense Amplifier-Based Pass Transistor Logic (SAPTL) with emphases on high energy-delay efficiency. The multiplier is targeted for an async multi-core System-On-Chip (SOC). This attribute is achieved by simplifying and optimizing the NMOS pass transistor stacks and decision-making C-element, therein to reduce the circuit area overheads and transistor switching’s in SAPTL. Based on the simulations (@1V, 65nm CMOS process), the async 16×16-bit pipelined multiplier based on our proposed SAPTL approach features, on average, 31% shorter delay, 21% lower energy/operation achieving a total of 46% lower energy-delay product, and 16% lesser number of transistors when compared to the reported SAPTL approaches. BV025VLSI13 DESIGN AND SIMULATION OF HYBRID SET-MOS PASS TRANSISTOR LOGIC BASED UNIVERSAL LOGIC GATES Abstract—In order to improve density of integration in VLSI chips and to ensure ultra low power dissipation Co-design of MOS transistor along with Single electron transistor is considered as one of the best option to work with. In the present work we have designed universal logic gates using hybrid SET-MOS based pass transistor logic. The logic gates are consists of one Single electron transistor and one NMOS transistor, both are working as pass transistors. In this paper we have designed NAND and NOR logic gates by providing inputs in their original and complemented form to the different nodes of the pass transistors depending upon the realization of that particular logic gate.In order to improve density of integration in VLSI chips and to ensure ultra low power dissipation Co-design of MOS transistor along with Single electron transistor is considered as one of the best option to work with. In the present work we have designed universal logic gates using hybrid SET-MOS based pass transistor logic. The logic gates are consists of one Single electron transistor and one NMOS transistor, both are working as pass transistors. In this paper we have designed NAND and NOR logic gates by providing inputs in their original and complemented form to the different nodes of the pass transistors depending upon the realization of that particular logic gate. BV026VLSI13 DIFFERENTIAL HIGH SPEED ULTRA LOW-VOLTAGE PASS TRANSISTOR BOOLEAN LOGIC In this paper we present high-speed and ultra low-voltage pass transistor. The delay of the proposed pass transistors are less than 6% of conventional CMOS pass transistors operating at supply voltages down to 200mV . The pass transistor logic presented can be used to implement low-voltage high-speed serial adders. The simulated data provided is obtained using Cadence and 90nm TSMC CMOS process. BV027VLSI14 IMPLEMENTATION OF AREA AND ENERGY EFFICIENT FULL ADDER CELL Abstract-This paper presents a low power full adder cell designed with transmission gate and pass-transistor logic styles that lead to have a reduced area, power and delay. We compared 28T conventional CMOS full-adders to 14T and 16T full adder cell, in terms of speed, power consumption and area. All the full adders were designed with a O.25um CMOS technology, and were tested using a tannerv13.0 .After simulating CMOS and pass transistors based full adder ,compared the average power consumption.16T based Full adder consumed 98% less power compared to 28T conventional CMOS full adder.This paper presents a low power full adder cell designed with transmission gate and pass-transistor logic styles that lead to have a reduced area, power and delay. We compared 28T conventional CMOS full-adders to 14T and 16T full adder cell, in terms of speed, power consumption and area. All the full adders were designed with a O.25um CMOS technology, and were tested using a tannerv13.0 .After simulating CMOS and pass transistors based full adder ,compared the average power consumption.16T based Full adder consumed 98% less power compared to 28T conventional CMOS full adder. BV028VLSI10 A 10-BIT LOW-POWER SMALL-AREA HIGH-SWING CMOS DAC Abstract—The design and measurements of a prototype general purpose digital to analog converter for readout systems in high energy physics experiments are presented. The main goals for the proposed DAC are low power consumption, small die area and high-swing voltage output. The 10-bit DAC design is based on a current steering architecture which includes a high-swing class AB output amplifier. The prototype ASIC is fabricated using 2P4M technology. Measurements of maximum differential 0.35 (DNL) and integral (INL)The design and measurements of a prototype general purpose digital to analog converter for readout systems in high energy physics experiments are presented. The main goals for the proposed DAC are low power consumption, small die area and high-swing voltage output. The 10-bit DAC design is based on a current steering architecture which includes a high-swing class AB output amplifier. The prototype ASIC is fabricated using 2P4M technology. Measurements of maximum differential 0.35 (DNL) and integral (INL) nonlinearity both show 0.42 LSB. The total power consumption is below 0.6 mW while the core area is 0.18mm2. BV029VLSI14 LOW-POWER PULSE-TRIGGERED FLIP-FLOP DESIGN BASED ON A SIGNAL FEED-THROUGH SCHEME Abstract— In this brief, a low-power flip-flop (FF) design featuring an explicit type pulsetriggered structure and a modified true single phase clock latch based on a signal feedthrough scheme is presented. The proposed design successfully solves the long discharging path problem in conventional explicit type pulse-triggered FF (P-FF) designs and achieves better speed and power performance. Based on post-layout simulation results using TSMC CMOS 90-nm technology, the proposed design outperforms the conventional P-FF design data-close-to-output (ep-DCO) by 8.2% in data-to-Q delay. In the mean time, the performance edges on power and powerdelay-product metrics are 22.7% and 29.7%, respectively. In this brief, a low-power flip-flop (FF) design featuring an explicit type pulsetriggered structure and a modified true single phase clock latch based on a signal feedthrough scheme is presented. The proposed design successfully solves the long discharging path problem in conventional explicit type pulse-triggered FF (P-FF) designs and achieves better speed and power performance. Based on post-layout simulation results using TSMC CMOS 90-nm technology, the proposed design outperforms the conventional P-FF design data-close-to-output (ep-DCO) by 8.2% in data-to-Q delay. In the mean time, the performance edges on power and powerdelay-product metrics are 22.7% and 29.7%, respectively. BV030VLSI13 DESIGN OF LOW POWER SEQUENTIAL CIRCUIT USING CLOCKED PAIR SHARED FLIP FLOP Abstract— The clock system consisting of clock distribution networks and sequential elements is most power consuming VLSI components. Reductions of flip flop, power consumption have a deep impact on the total power consumption. Since power consumption is a major bottleneck of system performance, the clock load should be reduced to reduce the power consumption. The clock distribution network distributes the clock signal from a common point to all the elements that need it. Since this function is vital to synchronous system, much attention has been given to the characteristics of these clock signal and the electrical networks used in their distribution. In synchronous system clock distribution networks consumes a large amount of total power because of high operation frequency of highest capacitance. An effective way to reduce capacity of clock load is by minimizing number of clocked transistor. In low swing differential capturing flip flop system clock distribution networks consumes a large amount of chip power and there exist a more number of clocked transistor. Hence by a novel approach, clocked paired shared flip flop local clocked transistors. The clock system consisting of clock distribution networks and sequential elements is most power consuming VLSI components. Reductions of flip flop, power consumption have a deep impact on the total power consumption. Since power consumption is a major bottleneck of system performance, the clock load should be reduced to reduce the power consumption. The clock distribution network distributes the clock signal from a common point to all the elements that need it. Since this function is vital to synchronous system, much attention has been given to the characteristics of these clock signal and the electrical networks used in their distribution. In synchronous system clock distribution networks consumes a large amount of total power because of high operation frequency of highest capacitance. An effective way to reduce capacity of clock load is by minimizing number of clocked transistor. In low swing differential capturing flip flop system clock distribution networks consumes a large amount of chip power and there exist a more number of clocked transistor. Hence by a novel approach, clocked paired shared flip flop local clocked transistors. BV031VLSI13 CLOCK GATING BASED ENERGY EFFICIENT ALU DESIGN AND IMPLEMENTATION ON FPGA Abstract— In this paper, latch free clock gating techniques is applied in ALU to reduce clock power and dynamic power consumption of ALU. Clock power is 50%, 41.46%, 51.30%, 55.15% and 55.78% of total dynamic power when device operating frequency is 100MHz, 1GHz, 10GHz, 100GHz and 1 THz. After implementation of clock gating techniques in ALU, Clock power reduces to 17.85%, 23.39%, 26.49% and 27.19% of total dynamic power, when device operating frequency is 1GHz, 10GHz, 100GHz and 1 THz. On 1 THz operating frequency, when we use clock gating, there are 72.77% reduction in clock power, 38.88% In this paper, latch free clock gating techniques is applied in ALU to reduce clock power and dynamic power consumption of ALU. Clock power is 50%, 41.46%, 51.30%, 55.15% and 55.78% of total dynamic power when device operating frequency is 100MHz, 1GHz, 10GHz, 100GHz and 1 THz. After implementation of clock gating techniques in ALU, Clock power reduces to 17.85%, 23.39%, 26.49% and 27.19% of total dynamic power, when device operating frequency is 1GHz, 10GHz, 100GHz and 1 THz. On 1 THz operating frequency, when we use clock gating, there are 72.77% reduction in clock power, 38.88% reduction in IOs power and 44% reduction in dynamic power in compare to power consumption without using clock gating techniques. Target device is 90-nm Spartan-3. There is 14.57% reduction in junction temperature on 10GHz operating frequency in compare to temperature without using clock gating techniques. Clock gating saves power but increases over all area. There is 32.35%, 37.84%, 43.31% and 44% reduction in dynamic current when we use clock gate on 1GHz, 10GHz, 100GHz and 1THz operating frequency respectively. BV032VLSI13 DESIGN OF A LOW-POWER PULSE-TRIGGERED FLIP-FLOP WITH CONDITIONAL CLOCK TECHNIQUE Abstract—Flip-flops are basic sequential elements in digital circuits and they have a deep impact on the performance of the circuits. In order to reduce the redundant transitions at internal nodes of the flip-flop, a conditional clock technique is proposed, and then aFlip-flops are basic sequential elements in digital circuits and they have a deep impact on the performance of the circuits. In order to reduce the redundant transitions at internal nodes of the flip-flop, a conditional clock technique is proposed, and then a conditional clock pulse-triggered flip-flop (CCFF) based on this technique is designed. In CCFF, the clock is blocked when the input remains unchanged so that the internal nodes will not switch with the clock, which reduces the power consumption effectively. Based on the TSMC 0.18μm technology, the post-layout simulation results show that the proposed CCFF has an obvious advantage in power consumption when the data switching activity factor is below 50% as compared with other state-of-the-art pulse-triggered flip-flops, and the power saving is more than 50% when the activity factor is 10%. BV033VLSI13 REAL TIME FPGA IMPLEMENTATION OF BRUSHLESS DC MOTOR CONTROL USING SINGLE CURRENT SENSOR Abstract— In modern industry power consumption is becoming one of the most important In modern industry power consumption is becoming one of the most important constraints during the development phase of the product. In motor industry, significant part of the power consumption improvement can be done in motor control. Brushless dc (BLDC) motor drives are penetrating the market rapidly. Heating, ventilation and air conditioning (HVAC) systems use conventional motor drive technology and the machines found in these devices are characterized by low efficiency and high maintenance. BLDC motor drives are characterized by higher efficiency, lower maintenance and higher cost. This paper presents the analysis, design, and implementation of a cost-effective control technique for a low cost solution, six switch threephase inverter brushless dc motor drive using single current sensor for current control. Various parameters defined optimization path for target drive solution. Also, basic framework for low cost BLDC control IC is presented. The controller is modeled and the concept is proven using simulator. Then the verification and feasibility study are done by using field-programmable gate array prototyping on the custom board made for this research. Final simulation results along with prototype operation measurements are presented as well. BV034VLSI13 HIGH PERFORMANCE LOW POWER DUAL EDGE TRIGGERED STATIC D FLIPFLOP Abstract—In this paper a low-power double-edge triggered static flip-flop (DETSFF) suitable for low-power and high performance applications is presented. The designed DETFF is verified at gpdk 180nm-1.8V CMOS technology. Comparison with some of the latest DETFFs shows that the proposed DETSFF can achieve the lowest power consumption, lowest clock to Q delay and thus Power-delay-product (PDP). Moreover, the proposed DETSFF comprises of only 15 transistors hence requires lesser number of transistors and thus requires lesser overall silicon area.In this paper a low-power double-edge triggered static flip-flop (DETSFF) suitable for low-power and high performance applications is presented. The designed DETFF is verified at gpdk 180nm-1.8V CMOS technology. Comparison with some of the latest DETFFs shows that the proposed DETSFF can achieve the lowest power consumption, lowest clock to Q delay and thus Power-delay-product (PDP). Moreover, the proposed DETSFF comprises of only 15 transistors hence requires lesser number of transistors and thus requires lesser overall silicon area. BV035VLSI13 DESIGN OF LOW POWER PULSED FLIP-FLOP USING SLEEP TRANSISTOR SCHEME Abstract In this paper, a novel low power pulsed flip-flop (P-FF) design featuring a sleep transistor scheme is proposed. In order to improve the leakage robustness for sub-90nm In this paper, a novel low power pulsed flip-flop (P-FF) design featuring a sleep transistor scheme is proposed. In order to improve the leakage robustness for sub-90nm low clock load dynamic flip-flops, a novel sleep transistor scheme is proposed. The scheme is implemented using CMOS 90nm technology file in Synopsis HSPICE. As compared to the conventional pulse triggered flip-flops, the proposed sleep transistor based P-FF design features best power-delay-product performance. The average power and leakage power is reduced without degrading the overall performance. BV036VLSI14 A NEW STRUCTURE OF LOW-POWER AND LOW-VOLTAGE DOUBLE-EDGE TRIGGERED FLIP-FLOP Abstract: In this paper a novel low-power double-edgetriggered flip-flop is introduced. Double-edge triggered Flip-Flops have the data signal changes on both the clock edges. Thus, low swing clock results in lower power consumption and the data throughout are In this paper a novel low-power double-edgetriggered flip-flop is introduced. Double-edge triggered Flip-Flops have the data signal changes on both the clock edges. Thus, low swing clock results in lower power consumption and the data throughout are preserved. Today, the leakage current has become a critical feature for integrated circuit (IC) designers because it leads to more power consumption. So in this paper some methods have been presented to control the leakage current. The proposed circuit is simulated in 0.35 μm CMOS technology with the power supply of 1.5V. The simulations are carried out by applying HSPICE software. The results of the proposed circuit show 180nW power dissipation. The number of clock transistors decrease which in turn results in lower leakage current, hence the power consumption reduces. BV037VLSI13 DESIGN OF SEQUENTIAL CIRCUITS IN MULTILAYER QCA STRUCTURE Abstract—This work targets developing sequential circuits in QCA under multilayer framework. The main goal is to build an efficient methodology to achieve high deviceThis work targets developing sequential circuits in QCA under multilayer framework. The main goal is to build an efficient methodology to achieve high device density as well as minimum delay in logic realization. This is the rst attempt in its kind of design with active QCA multilayer. The synthesis of conventional SR, JK, D and T ip-ops is reported following the multilayer QCA technology. The characterization of ip-ops is done with achievement of 100% fault tolerance under any kind of additional cell deposition QCA defect. It is established that the proposed multilayer design achieves 77% improvement in device density simultaneously with 50% improvement in delay than that of the existing conventional design approaches. The proposed design further achieves the minimum clock zone (3-clock) desired for sequential logic in QCA technology. BV038VLSI14 DESIGN AND ANALYSIS OF A SIMPLE D FLIP-FLOP BASED SEQUENTIAL LOGIC CIRCUITS FOR QCA IMPLEMENTATION Abstract—Quantum-dot Cellular Automata (QCA) is one of the emerging computing paradigms. Its advantages such as smaller size, lower power consumption and faster speed are very attractive. QCA performs highly dense computing that could be realized in a variety of material systems. It is presently being investigated as an alternative to CMOS VLSI. In conventional digital systems the information is transferred from one place to another by means of electrical current, while as QCA cells transfer information by propagating a polarization state. This paper proposes a detailed design and simulation of a simple D flip-Quantum-dot Cellular Automata (QCA) is one of the emerging computing paradigms. Its advantages such as smaller size, lower power consumption and faster speed are very attractive. QCA performs highly dense computing that could be realized in a variety of material systems. It is presently being investigated as an alternative to CMOS VLSI. In conventional digital systems the information is transferred from one place to another by means of electrical current, while as QCA cells transfer information by propagating a polarization state. This paper proposes a detailed design and simulation of a simple D flipflop based sequential logic circuits like shift register, ring counter and modulo n counter circuits for quantum-dot cellular automata. The proposed designs are based on the D-type flip-flop (DFF) device. A QCA binary wire with four clocking zones can be used to implement a DFF. The aim is to maximize the circuit density and focus on a layout that is minimal in its use of cells. BV039VLSI14 LOW STATIC AND DYNAMIC POWER MTCMOS BASED 12T SRAM CELL FOR HIGH SPEED MEMORY SYSTEM Abstract— This paper focuses on the static and dynamic power dissipations and power delay product of a proposed novel low power MTCMOS based 12T SRAM cell. In the proposed structure two voltage sources are used, one connected with the Bit line and the This paper focuses on the static and dynamic power dissipations and power delay product of a proposed novel low power MTCMOS based 12T SRAM cell. In the proposed structure two voltage sources are used, one connected with the Bit line and the other one connected with the Bit bar line in order to reduce the swing voltage at the output nodes of the bit and the bit bar lines. Reduction in swing voltage causes the reduction in dynamic power dissipation during switching activity. Because of MTCMOS technology, the SRAM cell is having low VT (LVT) transistors and there are two high VT (HVT) sleep transistors as well. Sleep transistors and a LVT Transmission gate (TG) in conjunction are used for reducing the wake up power during transition from sleep mode to active mode and sleep power during transition from sleep mode to active mode for writing operations of the SRAM cell. This reduces the static power dissipation of the SRAM cell. Simulation results of static and dynamic power dissipations and power delay product of the proposed SRAM cell have been determined and compared to those of some other exiting models of SRAM cell. The proposed SRAM cell dissipates less dynamic power at different frequencies, less static power during transition modes. Simulation has been done in 45nm CMOS environment with the help of Microwind 3.1. BV040VLSI14 LEAKAGE POWER REDUCTION IN DATA DRIVEN DYNAMIC LOGIC CIRCUITS Abstract—In this paper, data-driven dynamic logic and its’variant split-path data-driven dynamic logic circuits are analysed for dynamic and static power consumption. A new lowpower methodology is introduced in order to reduce the leakage current while maintainingIn this paper, data-driven dynamic logic and its’variant split-path data-driven dynamic logic circuits are analysed for dynamic and static power consumption. A new lowpower methodology is introduced in order to reduce the leakage current while maintaining the speed advantages of the data driven dynamic logic. A sleep switch transistor is used in the data driven dynamic circuits in order to force a sleep mode asynchronously. An additional power gating transistor is used to avoid the possible short-circuit paths during idle mode. The proposed circuits are compared against the conventional dynamic logic that uses dualV t sleep switch transistors for reduced leakage. 45nm technology has been used to implement the designs and they have been tested using ripple carry adders. The results demonstrate that, with the proposed circuits, leakage power can be reduced by more than 90%, with minimal impact on the speed and dynamic power consumption. Split-path datadriven dynamic logic offers the best speed and power-delay product among the dynamic logic circuits. BV041VLSI14 QCA BASED SEQUENTIAL AND COMBINATIONAL CIRCUIT DESIGN AND IMPORTANCE OF PARASITIC COMPONENTS AbstractAs the scaling of transistors has reached its nadir(6), (7), the valid replacement for the CMOS technology to achieve further advancements in the circuits, on the parameters of low power and area occupancy has become an immediate necessity. QCA is one of the greatest potential device technologies ever proposed till date, for the replacement of CMOS Technology. This paper presents the basic theory of Quantum dots with the technology involved in its fabrication, followed by the introduction of QCA including its fundamental concepts i.e. polarization and clocking and, its basic gate(inverter, majority gate) implementations. The working mechanism of complex circuit is given deep glance and, the problems faced during their implementation and working are identified. JK Flip-Flop is used as an example of complex circuitry to understand mechanism and identify problems. At last, As the scaling of transistors has reached its nadir(6), (7), the valid replacement for the CMOS technology to achieve further advancements in the circuits, on the parameters of low power and area occupancy has become an immediate necessity. QCA is one of the greatest potential device technologies ever proposed till date, for the replacement of CMOS Technology. This paper presents the basic theory of Quantum dots with the technology involved in its fabrication, followed by the introduction of QCA including its fundamental concepts i.e. polarization and clocking and, its basic gate(inverter, majority gate) implementations. The working mechanism of complex circuit is given deep glance and, the problems faced during their implementation and working are identified. JK Flip-Flop is used as an example of complex circuitry to understand mechanism and identify problems. At last, the solutions for the identified problems are provided. The output waveforms are provided to demonstrate the behavior of faulty as well as the modified fault free circuits. These designs are captured and simulated using a designing tool called QCA Designer. BV042VLSI14 LOW POWER DUAL EDGE TRIGGERED FLIP-FLOP AbstractA new technique for pulse generation circuit of dual edge triggered flip flop for low power is presented in this paper which enables the flip flop to be operated at 1.2 V. By incorporating a new fast latch and employing conditional precharging, dual edge triggered flip flop is capable of achieving low power consumption that has smaller delay. According to simulation on Spectre simulator, it has been observed that total power consumption of proposed flip flop at 0.67 switching activity is 30.16 % and 27.36 % less than that of previous A new technique for pulse generation circuit of dual edge triggered flip flop for low power is presented in this paper which enables the flip flop to be operated at 1.2 V. By incorporating a new fast latch and employing conditional precharging, dual edge triggered flip flop is capable of achieving low power consumption that has smaller delay. According to simulation on Spectre simulator, it has been observed that total power consumption of proposed flip flop at 0.67 switching activity is 30.16 % and 27.36 % less than that of previous arts DSPFF and SCDFF respectively. Clock-gated sense-amplifier is incorporated to reduce power consumption at low switching activity. Proposed flip-flop is capable to reduce Clock to output delay up to 44 % of that of DSPFF. BV043VLSI14 DESIGN OF A 4-BIT ADDER USING REVERSIBLE LOGIC IN QUANTUM-DOT CELLULAR AUTOMATA (QCA) Abstract— Both quantum-dot cellular automata (QCA) and reversible logic are emerging technologies that are promising alternatives to overcoming the scaling and heat dissipation issues, respectively, in the current CMOS designs. Here, the fundamentals of QCA and reversible logic are studied; the feasibility of incorporating reversible logic in QCA designs is also demonstrated. Based on two existing designs, an improved version of the reversible gates, namely the Feynman Gate and the Toffoli Gate, were implemented in QCA technology using QCA Designer. The proposed design of the QCA-based Feynman Gate is faster by 1⁄2 cycle as compared to the existing design; while the proposed Toffoli Gate has the same latency as the existing design but it is readily to be cascaded into a more complex design. A 4-bit ripple carry adder in QCA is then designed using the proposed Feynman and Toffoli gates to realize a reversible QCA full adder. This 4-bit QCA adder with reversible logic consists of 2030 QCA cells, has a latency of 7 clock cycles and 8 garbage outputs. Both quantum-dot cellular automata (QCA) and reversible logic are emerging technologies that are promising alternatives to overcoming the scaling and heat dissipation issues, respectively, in the current CMOS designs. Here, the fundamentals of QCA and reversible logic are studied; the feasibility of incorporating reversible logic in QCA designs is also demonstrated. Based on two existing designs, an improved version of the reversible gates, namely the Feynman Gate and the Toffoli Gate, were implemented in QCA technology using QCA Designer. The proposed design of the QCA-based Feynman Gate is faster by 1⁄2 cycle as compared to the existing design; while the proposed Toffoli Gate has the same latency as the existing design but it is readily to be cascaded into a more complex design. A 4-bit ripple carry adder in QCA is then designed using the proposed Feynman and Toffoli gates to realize a reversible QCA full adder. This 4-bit QCA adder with reversible logic consists of 2030 QCA cells, has a latency of 7 clock cycles and 8 garbage outputs. BV044VLSI14 A 24-TRANSISTOR STATIC FLIP-FLOP CONSISTING OF NORS AND INVERTERS FOR LOW-POWER DIGITAL VLSIS Abstract— In this paper, we propose a low-power circuit-shared static flip-flop (CS2FF) for extremely low power digital VLSIs. The CS2FF consists of five static NORs and two inverters (INVs). The CS2FF utilizes a positive edge of a buffered clock signal, which is generated from a root clock, to take data into a master latch and a negative edge of the root clock to hold the data in a slave latch. The total number of transistors is only 24, which is the same as the conventional tri-state buffer based flip flop (TBFF) used in the most standard cell libraries. SPICE simulations in 0.18-μm standard CMOS process demonstrated that our proposed CS2FF achieved clock-to-Q delay of 17.4 ns, setup time of 5.91 ns, hold time of 1.17 ns, and In this paper, we propose a low-power circuit-shared static flip-flop (CS2FF) for extremely low power digital VLSIs. The CS2FF consists of five static NORs and two inverters (INVs). The CS2FF utilizes a positive edge of a buffered clock signal, which is generated from a root clock, to take data into a master latch and a negative edge of the root clock to hold the data in a slave latch. The total number of transistors is only 24, which is the same as the conventional tri-state buffer based flip flop (TBFF) used in the most standard cell libraries. SPICE simulations in 0.18-μm standard CMOS process demonstrated that our proposed CS2FF achieved clock-to-Q delay of 17.4 ns, setup time of 5.91 ns, hold time of 1.17 ns, and power dissipation of 15.4 nW at 1-MHz clock frequency and 0.5-V power supply. The physical design area increased by 21% and power dissipation was reduced by 26% compared with those of conventional TBFF. Our proposed CS2FF can operate at 0.347 V with extremely low power of 6.61 nW, 33% less than that of TBFF. BV045VLSI14 A NOVEL RATIOED LOGIC STYLE FOR FASTER SUBTHRESHOLD DIGITAL CIRCUITS BASED ON 90 NM CMOS AND BELOW Abstract—An innovative logic style is proposed to achieve faster logic propagation in subthreshold operation: the Active Controlled Ratioed Logic (ACRL). It is an complete improvement and optimization from previous ratioed logic styles with pull-up current control and modified branches tailored to very-low supply voltage and ultra-low power.An innovative logic style is proposed to achieve faster logic propagation in subthreshold operation: the Active Controlled Ratioed Logic (ACRL). It is an complete improvement and optimization from previous ratioed logic styles with pull-up current control and modified branches tailored to very-low supply voltage and ultra-low power. Even without proper control of its load current at the pre-drive stage, the active power of ACRL cells can be suppressed to a comparable magnitude of static CMOS logic cells leakage. General logic cells and complex circuit designs were fabricated in 90 nm CMOS technology. In measurement they are 30-70% faster than those of static and dynamic CMOS styles, and with lower power when the logic activity rises to a certain level. BV046VLSI14 EFFICIENT REALIZATION OF DIGITAL LOGIC CIRCUIT USING QCA MULTIPLEXER Abstract-Quantum-dot cellular Automata (QCA), a viable alternative to current CMOS, is gaining its prominence in digital circuit due to its very high device density and clocking speed. This work targets design of efficient logic circuits based on QCA multiplexer. The design capability of the multiplexer in QCA is investigated implementing XOR, XNOR logic gate and arithmetic logic unit. Further, efficient sequential circuits like D latch, T latch, D flip-flop, Scan flip-flop, shift registers are designed using QCA multiplexer. Results obtained supports the fact that the proposed designs achieve significant improvement in terms of device density, cell count as well as clock delay than that of the other previous designs.Quantum-dot cellular Automata (QCA), a viable alternative to current CMOS, is gaining its prominence in digital circuit due to its very high device density and clocking speed. This work targets design of efficient logic circuits based on QCA multiplexer. The design capability of the multiplexer in QCA is investigated implementing XOR, XNOR logic gate and arithmetic logic unit. Further, efficient sequential circuits like D latch, T latch, D flip-flop, Scan flip-flop, shift registers are designed using QCA multiplexer. Results obtained supports the fact that the proposed designs achieve significant improvement in terms of device density, cell count as well as clock delay than that of the other previous designs. BV047VLSI14 ONE-BIT NON-VOLATILE MEMORY CELL USING MEMRISTOR AND TRANSMISSION GATES Abstract—In recent researches, much emphasis has been placed in developing non-volatileIn recent researches, much emphasis has been placed in developing non-volatile memories as candidates for replacement of volatile memories. Apart from non-volatility, memristive devices also have high switching speed, low energy consumption, and small device size. In this article, a novel one-bit memory cell using two transmission gates and one memristor (2TG1M) is proposed. SPICE simulations were performed to compare energy requirements per one-bit memory cell between the proposed memory cell and the conventional volatile one-bit SRAM cell. Simulations show that the SRAM memory cell requires between 73.034 pJ and 12.433 nJ to retain logic information for 10 years, while the proposed memory cell requires less than 1 pJ to hold logic information for up to 10 years. The proposed memory cell is also simulated against the popular one transistor one memristor (1T1M) non-volatile memory cell to show faster switching speed by 1.5 times. This work concludes the advantages of the proposed 2TG1M non-volatile memory cell against volatile memory in terms of energy requirements, and against non-volatile memory in terms of switching speed. BV048VLSI14 A LOW POWER CMOS FLIP-FLOP FOR HIGH PERFORMANCE PROCESSORS BV049VLSI14 AN IMPLEMENTATION OF 1BIT LOW POWER FULL ADDER BASED ON MULTIPLEXER AND PASS TRANSISTOR LOGIC Abstract –A novel implementation of 1 bit full adder based on multiplexer cell is being proposed. This paper presents the design of low power full adder based on XOR pass transistor logic and transmission gate for carry. To reduce the transition activity and chargeA novel implementation of 1 bit full adder based on multiplexer cell is being proposed. This paper presents the design of low power full adder based on XOR pass transistor logic and transmission gate for carry. To reduce the transition activity and charge recycling capability we have not connected power supply rail directly instead of that inputs are given directly and this result in great amount of reduction in power consumption. Power is decreased to a substantial amount while transistor count has gone up to 14T rather 12T. Exhaustive and intensive Tanner SPICE simulation is done and it shows that there is saving of power supply by the factor of 30% as compare to 10T and 26% reduction in power as compare to conventional 28-T CMOS adder[1]-[2]. BV050VLSI14 LOW-POWER COMPARATOR DESIGN BASED ON CMOS DYNAMIC LOGIC CIRCUIT Abstract: Here a new design of comparator is proposed which is based half precharged CMOS dynamic logic just by introducing few more transistors as precharge, transmission transistor which not only reduces the leakage current but improves the power consumption of circuit. For simulation, designing Microwind & DSCH software with 120/70 nm technology is used. Here a new design of comparator is proposed which is based half precharged CMOS dynamic logic just by introducing few more transistors as precharge, transmission transistor which not only reduces the leakage current but improves the power consumption of circuit. For simulation, designing Microwind & DSCH software with 120/70 nm technology is used. BV051VLSI14 POWER ANALYSIS AND COMPARISON OF CLOCK GATED TECHNIQUES IMPLEMENTED ON A 16-BIT ALU Abstract— Power dissipation is a bottleneck in the design of low power electronic devices that, operate at high frequencies. Hence, the clock signal is a major source of power dissipation. The technique clock gating at the architecture level can be implemented to reduce the dynamic and clock power. In this paper, the authors aim at implementing, analyzing and comparing the various resource power using clock gating techniques to a 16bit ALU on a 45nm SPARTAN6 FPGA board. The two clocking gates proposed and used in the design are namely: DEMUX and AND gate, which provide clock input to only one functional module that is either arithmetic or logical block, while the other is put OFF. The complete design is simulated using QuestaSim, synthesized using Precision tool and the power analysis is performed using Xpower analyzer of ISE13.2. The results obtained demonstrate that the clock, signal and the logic power for the two techniques is nearly same. While the IO and dynamic power using AND clocking gate has the power reduction of 50% and 45% respectively. Thus, the AND clock gating technique can be used in the design to optimize power and area. Power dissipation is a bottleneck in the design of low power electronic devices that, operate at high frequencies. Hence, the clock signal is a major source of power dissipation. The technique clock gating at the architecture level can be implemented to reduce the dynamic and clock power. In this paper, the authors aim at implementing, analyzing and comparing the various resource power using clock gating techniques to a 16bit ALU on a 45nm SPARTAN6 FPGA board. The two clocking gates proposed and used in the design are namely: DEMUX and AND gate, which provide clock input to only one functional module that is either arithmetic or logical block, while the other is put OFF. The complete design is simulated using QuestaSim, synthesized using Precision tool and the power analysis is performed using Xpower analyzer of ISE13.2. The results obtained demonstrate that the clock, signal and the logic power for the two techniques is nearly same. While the IO and dynamic power using AND clocking gate has the power reduction of 50% and 45% respectively. Thus, the AND clock gating technique can be used in the design to optimize power and area. BV052VLSI15 SELF DRIVEN PASS-TRANSISTOR BASED LOW-POWER PULSE TRIGGERED FLIPFLOP DESIGN Abstract— In this paper, self driven pass-transistor based low power pulse triggered flip-flop design is conferred. In this configuration, the creation of clock pulse is implemented with pass transistor based two input AND gate for reducing the discharging path and improve the speed, reduce the circuit complexity. In the proposed design input to output driving path inverter is deleted and the transistor is substituted with pass transistor logic. The pass transistor driven by generated clock pulse is utilized to drive the flip flop output. As compared to the conventional pulse triggered flip-flop, the proposed pulse triggered flipIn this paper, self driven pass-transistor based low power pulse triggered flip-flop design is conferred. In this configuration, the creation of clock pulse is implemented with pass transistor based two input AND gate for reducing the discharging path and improve the speed, reduce the circuit complexity. In the proposed design input to output driving path inverter is deleted and the transistor is substituted with pass transistor logic. The pass transistor driven by generated clock pulse is utilized to drive the flip flop output. As compared to the conventional pulse triggered flip-flop, the proposed pulse triggered flipflop design features are best speed, power and Power-Delay-Product (PDP) performance. It's maximum power saving against conventional pulse triggered flip-flop designs such as IPDCO, MHLFF, SCCER, CPE-PFF is up to 99.69%, 99.43%, 95.09%, 84.14% respectively at 100 MHZ input data rate. The proposed design is generated by using TSPICE CMOS 180nm process technology. BV053VLSI15 LOW-POWER CLOCK DISTRIBUTION USING A CURRENT-PULSED CLOCKED FLIP-FLOP Abstract—We propose a new paradigm for clock distribution that uses current, rather than voltage, to distribute a global clock signal with reduced power consumption. While currentmode (CM) signaling has been used in one-to-one signals, this is the first usage in a one-tomany clock distribution network. To accomplish this, we create a new high-performance current-mode pulsed flip-flop with enable (CMPFFE) using 45 nm CMOS technology. When the CMPFFE is combined with a CM transmitter, the first CM clock distribution network exhibits 62% lower average power compared to traditional voltage mode clocks.We propose a new paradigm for clock distribution that uses current, rather than voltage, to distribute a global clock signal with reduced power consumption. While currentmode (CM) signaling has been used in one-to-one signals, this is the first usage in a one-tomany clock distribution network. To accomplish this, we create a new high-performance current-mode pulsed flip-flop with enable (CMPFFE) using 45 nm CMOS technology. When the CMPFFE is combined with a CM transmitter, the first CM clock distribution network exhibits 62% lower average power compared to traditional voltage mode clocks. BV054VLSI15 IMPLEMENTATION OF LOW POWER FLIP FLOP DESIGN IN NANOMETER REGIME Abstract—In present digital circuits, low power consumption with high packaging density is always needed. The continuous reduction of MOSFET devices channel length causes an undesirable Short Channel Effects on the device parameters rendering large power dissipation. Increased leakage current with technology improvement requires tight control. In delay flip flop the storing of data get restricted due to leakage current which can limit flip flop from performing its operation. In this paper we have illustrated Single Edge Triggered 5T Delay flip flop design with leakage reduction technique in which the feedback path get removed that was present in the conventional Delay flip flop design. The proposed design had several advantages in comparison with the conventional D FF in terms of reduced transistors count, decreased leakage current, increases stability and high speed. We have considered further the Single Edge Triggered 5T DFF design using Self Voltage Level Control Technique in Cadence Virtuoso Tool at 45 nm technology. The result shows a tremendous reduction in leakage power nearly by 68% at 1volt supply in comparison with the conventional Set-Reset latch based DFF.In present digital circuits, low power consumption with high packaging density is always needed. The continuous reduction of MOSFET devices channel length causes an undesirable Short Channel Effects on the device parameters rendering large power dissipation. Increased leakage current with technology improvement requires tight control. In delay flip flop the storing of data get restricted due to leakage current which can limit flip flop from performing its operation. In this paper we have illustrated Single Edge Triggered 5T Delay flip flop design with leakage reduction technique in which the feedback path get removed that was present in the conventional Delay flip flop design. The proposed design had several advantages in comparison with the conventional D FF in terms of reduced transistors count, decreased leakage current, increases stability and high speed. We have considered further the Single Edge Triggered 5T DFF design using Self Voltage Level Control Technique in Cadence Virtuoso Tool at 45 nm technology. The result shows a tremendous reduction in leakage power nearly by 68% at 1volt supply in comparison with the conventional Set-Reset latch based DFF. BV055VLSI15 IMPLEMENTATION OF HIGH PERFORMANCE SRAM CELL USING TRANSMISSION GATE Abstract-Static Random Access Memory (SRAM) plays a most substantial role in the microprocessor world, but as the technology is scaling down in nanometers, leakage parameters and delay are the most common problems for SRAM cell which is basically designed for very low power application. Transmission gate is used to further reduced leakage current penetrating in the 8T SRAM cell. Comparative analysis is performed by usingStatic Random Access Memory (SRAM) plays a most substantial role in the microprocessor world, but as the technology is scaling down in nanometers, leakage parameters and delay are the most common problems for SRAM cell which is basically designed for very low power application. Transmission gate is used to further reduced leakage current penetrating in the 8T SRAM cell. Comparative analysis is performed by using transmission gate. This paper represents a method for design a variability aware SRAM cell. The proposed architecture of the TG8T SRAM cell is analogous to the standard 6T SRAM cell, theonly exception is that they possess full transmission gates which replace an access pass transistor. The paper studies the different parameters of TG8Twrite operation at 0.7 V like leakage current is 229.2fA, leakage power is 297.4nW, delay is 20.92ns and SNR is 4.77dB. This result performs on the cadence virtuoso tool at 45nm technology. BV056VLSI15 AN EFFICIENT DESIGN TECHNIQUE FOR LOW POWER DYNAMIC FEEDTHROUGH LOGIC WITH ENHANCED PERFORMANCE FOR WIDE FAN-IN GATES Abstract—This paper presents a new approach to high performance and low power circuit for wide fan-in gates using a new CMOS logic known as feedthrough logic (FTL). Feedthrough logic can improve the performance by partial evaluation in its computational block before getting a valid input. The FTL is more suited for that circuit which consists of a critical path of large cascaded inverting gates. FTL based circuits can perform better in both high fan-out and high frequency operations due to both dynamic power consumption and lower delay at the cost of area. The proposed circuit achieves a reduction in the average power. The comparison analysis has been carried out by simulating the logic circuit by 180 nm technology. The proposed modified FTL reduces total power consumption up to 13.25% in wide fan-in NAND gates and 99.9% in wide fan-in NOR gates. This model works more effectively in the case of NOR gates but creates more delay as compared to other proposed FTL models.This paper presents a new approach to high performance and low power circuit for wide fan-in gates using a new CMOS logic known as feedthrough logic (FTL). Feedthrough logic can improve the performance by partial evaluation in its computational block before getting a valid input. The FTL is more suited for that circuit which consists of a critical path of large cascaded inverting gates. FTL based circuits can perform better in both high fan-out and high frequency operations due to both dynamic power consumption and lower delay at the cost of area. The proposed circuit achieves a reduction in the average power. The comparison analysis has been carried out by simulating the logic circuit by 180 nm technology. The proposed modified FTL reduces total power consumption up to 13.25% in wide fan-in NAND gates and 99.9% in wide fan-in NOR gates. This model works more effectively in the case of NOR gates but creates more delay as compared to other proposed FTL models. BV057VLSI15 DYNAMIC THRESHOLD SOURCE COUPLED LOGIC WITH PUSHPULL TOPOLOGY FOR ULTRA LOW POWER APPLICATIONS Abstract— Subthreshold source coupled logic circuits (STSCL) are normally used for designing ultra-low power components and systems operating in the weak inversion (subthreshold) regime. This paper presents an implementation of a robust source coupled technique i.e. Dynamic threshold source coupled logic (DTSCL) with push pull amplifier at the output stage. The proposed circuit was analyzed to obtain minimum delay and power dissipation by varying the tail bias current. This circuit offered a very low power delay product (PDP) and was less sensitive to temperature and power supply variations. A tail bias current of the order of Pico amperes was capable of driving the circuit when implemented on 180nm CMOS technology. Measured results indicate that the simulated circuit offers a better performance for ultra-low power SCL circuits. Cadence virtuoso and Spectre simulation tools were used for simulating the circuit. Subthreshold source coupled logic circuits (STSCL) are normally used for designing ultra-low power components and systems operating in the weak inversion (subthreshold) regime. This paper presents an implementation of a robust source coupled technique i.e. Dynamic threshold source coupled logic (DTSCL) with push pull amplifier at the output stage. The proposed circuit was analyzed to obtain minimum delay and power dissipation by varying the tail bias current. This circuit offered a very low power delay product (PDP) and was less sensitive to temperature and power supply variations. A tail bias current of the order of Pico amperes was capable of driving the circuit when implemented on 180nm CMOS technology. Measured results indicate that the simulated circuit offers a better performance for ultra-low power SCL circuits. Cadence virtuoso and Spectre simulation tools were used for simulating the circuit. BV058VLSI15 DESIGN OF NOVEL INVERTER AND BUFFER IN QUANTUM-DOT CELLULAR AUTOMATA (QCA) Abstract–Quantum-dot Cellular Automata (QCA) is an emerging nanotechnology to reduce size as well as power consumption of switching devices for Very Large Integrated Circuits (VLSI). Moreover QCA circuits offer an advantage of very high device density, high speed,Quantum-dot Cellular Automata (QCA) is an emerging nanotechnology to reduce size as well as power consumption of switching devices for Very Large Integrated Circuits (VLSI). Moreover QCA circuits offer an advantage of very high device density, high speed, high fan out, and lower circuit complexity. The QCA based circuits have been used for implementations of basic logic gates like AND, OR, NOT as well as XOR/XNOR gates. This paper aims at the design of a programmable inverter/buffer using proposed XOR gate. The proposed circuit can be used as an inverter (NOT gate) or a buffer (pass gate). The programmable inverter/buffer has been designed and simulated based on intensive discrete arithmetic analysis. In addition, 2-bit and 3-bit programmable inverter/buffer has also been designed and implemented in this paper. The proposed design enjoys the features of small area, superior performance factors in respect of speed and circuit stability. The simulation results have been verified using QCADesigner tool version 2.0.3. BV059VLSI15 DESIGN AND ANALYSIS OF ODDAND EVEN-PARITY GENERATORS AND CHECKERS USING QUANTUM-DOT CELLULAR AUTOMATA (QCA) Abstract – Quantum-dot Cellular Automata (QCA) is an emerging technology for nano-scale computing. There is an ever increasing demand for reliable data transmission over telecommunication networking systems. The researchers are focusing on developing nanodevices that can detect/check errors during information communication. In this paper novel 3-bit oddand even-parity generators and checkers using QCA nanotechnology, is presented. The proposed techniques can be used to detect and check errors during information communication (message word). The parity generators and checkers have been Quantum-dot Cellular Automata (QCA) is an emerging technology for nano-scale computing. There is an ever increasing demand for reliable data transmission over telecommunication networking systems. The researchers are focusing on developing nanodevices that can detect/check errors during information communication. In this paper novel 3-bit oddand even-parity generators and checkers using QCA nanotechnology, is presented. The proposed techniques can be used to detect and check errors during information communication (message word). The parity generators and checkers have been designed based on QCA XOR/XNOR gates. The circuits present a simple design using homogenous layer of cells and effective technique to find errors in data transmission systems. The results of computer simulation tests carried on the proposed designs have confirmed the suitability of the proposed techniques. QCA Designer tool, ver. 2.0.3, has been used for the simulations carried out in this paper. BV060VLSI15 LOW POWER FLIP FLOP MERGING TECHNIQUE BY CRITICAL PATH DELAY ANALYSIS Abstract—Power consumed by clocking has taken a major part of the whole design circuit. Given a design, we can reduce its power consumption by replacing several flip-flops with some multi-bit flip-flop. This may affect the performance of the original circuit because of itsPower consumed by clocking has taken a major part of the whole design circuit. Given a design, we can reduce its power consumption by replacing several flip-flops with some multi-bit flip-flop. This may affect the performance of the original circuit because of its timing and placement capacity constraints. To overcome this problem efficiently, a technique combination table is built to enumerate possible combinations of flip-flops provided by a library. Finally, merging of flip-flops is done with help of co-ordination transformation and combination table. We can achieve better area reduction and power reduction by 37.65%. The implementation of flip flop merging is done in MODELSIM software and the power analysis through Quartus II.